Exascale Supercomputers Design Verification Engineer (RE12)
Location: Barcelona, Spain
Department: IT & E-Commerce
Salary: Salario competitivo
Contract: De duración indefinida
Our client is the leading supercomputing center in Spain. It houses one of the most powerful supercomputers in Europe, and is a hosting member of the PRACE European distributed supercomputing infrastructure. Their mission is to research, develop and manage information technologies in order to facilitate scientific progress. It combines HPC service provision and R&D into both computer and computational science (life, earth and engineering sciences) under one roof, and currently has over 650 staff from 49 countries.
Our client is looking for talented and motivated professionals with expertise in RTL Design Verification targeting ASICs and FPGAs for a European HPC accelerator. The design is based on RISC-V architecture. This is a NEW project to build an FPGA-based emulator for an energy-efficient Exascale system.
- You will use your design and verification expertise to verify complex digital designs.
- You will collaborate closely with design and verification engineers in active projects and perform hands-on verification.
- Using your UVM, SystemVerilog and problem-solving skills, you will build efficient and effective verification environments that exercise processor designs through their corner-cases and expose all types of bugs.
- You will be responsible for the full life cycle of verification, from verification planning to test execution, to collecting and closing coverage.
- Ph.D. in Electrical Engineering or Engineering degree or equivalent level of professional experience.
Essential Knowledge and Professional Experience:
-Experienced with the full verification life cycle from test planning to signoff.
-Knowledge of and experience with industry-standard simulators (Model/QuestaSim, VCS, etc.), revision control systems and regression systems.
-Experienced in all latest DV methodologies: Formal Verification, System Verilog and UVM, Assembly/C-based Verification, Low power Verification using UPF/CPF.
- Experienced in developing a DV plan based on Functional Specification, create and build the necessary verification test bench/infrastructure, develop tests and verify design.
- Strong debugging skills and able to work with design engineers to deliver functionally correct design blocks.
- Familiar with RTL coding using Verilog and overall design flow from Spec to Tapeout and mapping RTL to FPGAs.
- Experience with top-level and processor-based SOC and DLP (GPU/SIMD/Vector) verification.
- Strong scripting experience using scripting languages like Python, Perl, or Tcl.
- Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
- Familiarity with Linux.
- Agile development and open source development, deployment, and support, including GitHub or equivalent.
- Proficient in Microsoft Office applications or equivalent.
- Knowledge of processor and GPU architecture and design.
- Fluency in English is essential, Spanish is welcome.
- The candidate must be an effective communicator, multitask, and work well on collaborative designs.
- Keeps abreast of technology trends.
- Ability to think creatively.
- Ability to work independently and make decisions.
- Ability to take initiative, prioritize and work under set deadlines and pressure.
Our client offers a full-time contract (temporary 2-3 years renewable), a good working environment, a highly stimulating environment with state-of-the-art infrastructure, flexible working hours, extensive training plan, tickets restaurant, private health insurance, fully support to the relocation procedures
(+34) 93 231 00 00 (Ext. 282)