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Exascale Supercomputer ASIC Engineer (RE12)

Location: Barcelona, Spain
Department: IT & E-Commerce
Salary: Salario competitivo
Contract: De duración indefinida


Our client is the leading supercomputing center in Spain. It houses one of the most powerful supercomputers in Europe, and is a hosting member of the PRACE European distributed supercomputing infrastructure. Their mission is to research, develop and manage information technologies in order to facilitate scientific progress. It combines HPC service provision and R&D into both computer and computational science (life, earth and engineering sciences) under one roof, and currently has over 650 staff from 49 countries.


We are looking for talented and motivated professionals with expertise in ASIC design and IP integration for a European HPC accelerator. The design is based on RISC-V architecture. This is a NEW project to build an FPGA-based emulator for an energy-efficient Exascale system.

Key Duties

- You will use your design expertise to design and build complex digital designs focused on scalar processors, vector units, and/or other accelerators, including writing specifications.
- Design integration, logic synthesis and design optimization for area, timing and power.
- Developing front-end methodologies and tool flows.
- You will collaborate closely with design and verification engineers in active projects and perform hands-on design, writing RTL.
- Participating in chip bring-up and testing.


- Ph.D. in Electrical Engineering or Engineering degree or equivalent level of professional experience.

Essential Knowledge and Professional Experience:
- Modern in-order and out-of-order processor core and GPU designs, with expertise in one or more of the following areas: fetch, decode, branch prediction, renaming and scheduling, out-of-order execution, re-order buffer, integer, and floating-point execution, vector execution, load/store execution, caches, and memory subsystem.
- Experience with one or more, including RISC-V, Instruction Set Architectures (ISAs) and their implementation within in-order and out-of-order processor cores.
- High-speed low-power design techniques.
- Knowledge of logic synthesis and timing closure.
- SMP related topics such as coherency and consistency.
- Experience in taking ASIC (gate array, library-based, and/or full custom) designs through to production.
- Proficiency in Verilog/VHDL, Chisel and end-to-end design methodologies is required.
- RTL Design(Functional/Structural, Partitioning, Simulation, Regression, Modelsim, VCS, Design Compiler, Primetime, Microprocessor Architecture, Memory Coherency).
- Strong scripting/programming in C/C++, Tcl, Python, Perl/Csh.
- Strong analytic skills, familiarity with common signal processing structures (encoders, decoders, equalizers), experience with DSPs, MCUs, FPGAs, SoC, and low-power design will be considered a big plus.
- Low Power Design (clock gating, power gating, power grids, Power Artist, UPF, CPF).
- High-Speed DDR Controller (Memory Controller, CPU, SRAM L3 Cache, x86 or ARM CPU/bus architecture).
- DLP (GPU/SIMD/Vector) ASIC Hardware development a plus.
- Physical Layer Design(PHY, USB, HDMI, DDR, MIPI).
- SerDes Application(PHY Layer Protocol, SerDes PHY, ASIC EDA Models, Cadence Schematics).
- Digital Design for Mixed-Signal ASICs (PLL, Phase-Lock-Loop, LNA, OpAmp, ADC-DAC).
- Complex state machine design.
- Memory subsystem with multiple banking multiple reports, crossbar connection to computing elements.
- 3-D, 4-D descriptor-based DMA controller with out of order responses.
- 3rd Party IP integration experience.
- Agile development and open source development, deployment, and support, including GitHub or equivalent.
- Proficient in Microsoft Office applications or equivalent.
- Fluency in English is essential, Spanish is welcome.

- Effective communication, multitasking, and working well on collaborative designs.
- Keeping abreast on technology trends.
- Ability to think creatively.
- Ability to work independently and make decisions.
- Ability to take initiative, prioritize and work under set deadlines and pressure.


Our client offers a full-time contract (temporary 2-3 years renewable), a good working environment, a highly stimulating environment with state-of-the-art infrastructure, flexible working hours, extensive training plan, tickets restaurant, private health insurance, fully support to the relocation procedures


Judit López
(+34) 93 231 00 00 (Ext. 282)

Placement agency Nº 9900000357
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